Condensed CV
Publications
First author on two peer-reviewed conference papers and one workshop paper. Full references and BibTeX are on the publications page, and records on ORCID.
∗ Equal contribution.
Dr. DD: 1-Minimal Isolation of Failure Causes via Deferred Restarts
Aarush Kumbhakern, Feiyang Chen, Danushka Liyanage, Xi Wu, Mohammad Amin Alipour, Rahul Gopinath
IEEE International Symposium on Software Reliability Engineering (ISSRE) 2026 · Accepted
HyDRA: A Slug-Flow Microfluidic Architecture and Instruction Set
Aarush Kumbhakern, Bhargab Bikram Bhattacharya
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026 · Presented
Towards an Action-Centric Ontology for Cooking Procedures Using Temporal Graphs
Aarush Kumbhakern∗, Saransh Kumar Gupta∗, Lipika Dey, Partha Pratim Das
1st International Workshop on Multi-modal Food Computing (MMFood), co-located with ACM Multimedia 2025 · Published
Research experience
Visiting Student Researcher · University of Sydney
Nov 2023 – present · Remote · Advisor: Rahul Gopinath
I implemented, optimized and evaluated Dr. DD, which isolates failure causes while preserving 1-minimality, and built its replication package. On XML it ran 6.0× faster using 1.7% of
ddminY's oracle calls; mean reduction quality was comparable across benchmark families. I'm now working on reducing inputs without a supplied grammar, by learning their structure from the failure oracle itself.Undergraduate Researcher · Mphasis AI & Applied Tech Lab, Ashoka University
May 2025 – present · Sonipat, India · Advisor: Partha Pratim Das
I developed a temporal-graph ontology for cooking procedures, published at MMFood 2025 with equal-contribution credit, and extended it into a recipe DSL with a Python pipeline for LLM extraction, deterministic compilation, validation and interactive rendering.
Undergraduate Thesis · Ashoka University
Aug 2025 – Apr 2026 · Sonipat, India · Advisor: Bhargab B. Bhattacharya
I designed HyDRA, a programmable microfluidic architecture and instruction set, with a finite integer-state safety model, a static verification procedure and a soundness argument. Evaluation covers physical feasibility under stated assumptions.
Education
B.Sc. (Hons.) in Computer Science · Ashoka University
Sep 2022 – early 2027 (expected) · Sonipat, India · Four-Year Honours with Research · Biology minor
CGPA 3.63 / 4.00 through Spring 2026; coursework completes in December 2026. Thesis: HyDRA, grade A.
Engineering
Engineering Intern · Catalis Packaging Technologies Pvt. Ltd.
Nov 2023 – Jan 2024 · Vadodara, India
I built a Raspberry Pi gateway that polls machines over Modbus TCP, buffers readings in SQLite on a USB key and uploads them when the network allows; inserting or removing the key starts and stops it. I demonstrated it against machines and test benches and wrote the operator and technical documentation.
Honors, talks & teaching
Conference presentation of HyDRA, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2026.
Academic Excellence Award for the Best Undergraduate Thesis in Computer Science, Ashoka University, 2026.
Available, Reviewed and Reproducible artifact badges for Dr. DD's code and data, ISSRE 2026.
Teaching assistant, Lodha Genius Program, Ashoka University, May–June 2025: I mentored five early-high-school students through a month-long computational biology course and gave a lecture on version control for reproducible research.
Engineering International Scholar Award, University of Toronto, 2022: a merit entrance scholarship of CAD 140,000 over four years. Declined.